The invention relates to a dynamic-semiconductor memory.
A dynamic semiconductor memory in which all the read amplifiers are connected via in each case one transistor, connected as a resistor, to a common SANN line which has a line impedance and can be connected via a single common driver transistor (global SAN driver) to reference potential, and in which one SAN input of a respective read amplifier can be connected to reference potential via a respective further transistor, which can be driven from a column decoder via a bit-line selection signal, has been disclosed in the publication having the title "Decoded-Source Sense Amplifier For High-Density DRAM's" by Okamura et al. (Toshiba), from the Digest of Technical Papers from the 1989 Symposium on VLSI Circuits (pages 103 to 104). The transistors which are connected as resistors are provided in order that the read amplifiers are not driven significantly differently as a function of the geometric distance to the common driver transistor, as a result of the line impedance, and in order that certain mutual decoupling of the SAN inputs of the read amplifiers takes place. In this case, only one common driver transistor (global SAN driver) is required and not, as in the case of the invention, a plurality of existing local SAN drivers, but in each case one transistor connected as a resistor and one transistor driven by the column decoder are required for this purpose per read amplifier.
A further prior publication by Okamura et al. (IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, February 1990, pages 18-22) additionally discloses, for example, in each case four read amplifiers having to be connected to a common SANN line via a transistor connected as a resistor, and the SAN inputs of these read amplifiers having to be connected to reference potential via only one further transistor, which can be driven by the column decoder, in order to save chip area. However, for example, this has the disadvantage that only partial decoding is possible.
IEEE Journal of Solid-State Circuits, Vol. Sc-22, No. 5, October 1987, pages 651 to 656 discloses a semiconductor memory in which in each case one multi-phase SAN driver which is common (global) to all the read amplifiers is connected to one end of a common SANN line per word line block, and, in addition, a driver transistor is connected to the other end of the SANN line, the function of the driver transistor not, however, being dependent on bit-line selection signals and hence acting simultaneously on all the read amplifiers of a word line block.